DeepX Partners with Samsung for LPDDR5X-PIM AI Chips

DeepX is set to integrate Samsung Electronics' LPDDR5X-PIM technology into its upcoming AI chips. This strategic move aims to bring Processing-in-Memory (PIM) solutions to the commercial market by late 2026.

The collaboration addresses the critical bottleneck of data movement in AI systems. By processing data directly within memory, DeepX seeks to drastically improve energy efficiency and computational speed for edge devices.

Key Facts at a Glance

• Strategic Partnership: DeepX will utilize Samsung Electronics as the sole supplier for its PIM-enabled memory solutions.
• Hardware Specs: The new DX-M2 chip features 80 TOPS of算力 (trillion operations per second) built on a 2nm process node.
• Cost Efficiency: The target launch price for the DX-M2 is under $50, making high-end edge AI accessible.
• Future Roadmap: The subsequent DX-M3 chip targets 1000 TOPS performance using standardized LPDDR6-PIM.
• Technology Core: PIM reduces data transfer latency by performing calculations inside DRAM modules.
• Market Timing: Commercial deployment is scheduled around the 2026 K-AI Semiconductor Growth Forum timeline.

Breaking the Memory Wall with PIM Technology

Traditional AI accelerators struggle with the "memory wall," where the speed of computation is limited by how fast data can be moved from storage to the processor. Processing-in-Memory (PIM) technology fundamentally changes this architecture. It embeds dedicated data processors directly into the DRAM chips themselves.

This integration allows specific computational tasks to be offloaded from the main host processor to the memory module. Consequently, the system requires less data movement across the bus. Reduced data movement translates directly to lower power consumption and higher throughput.

For edge AI applications, such as autonomous vehicles or smart IoT sensors, energy efficiency is paramount. DeepX’s adoption of Samsung’s LPDDR5X-PIM positions it to lead this efficiency race. Unlike conventional setups that rely on separate high-bandwidth memory (HBM), PIM offers a compact and power-efficient alternative.

Why Samsung is the Exclusive Partner

Samsung Electronics currently stands as the only major supplier capable of providing mature LPDDR5X-PIM solutions. This exclusivity gives DeepX a unique competitive advantage but also creates dependency.

The synergy between DeepX’s logic chips and Samsung’s memory tech creates a cohesive ecosystem. This vertical integration minimizes compatibility issues and optimizes performance out of the box. Other competitors may face delays while waiting for broader industry standardization of PIM technologies.

The DX-M2: High Performance at Low Cost

The centerpiece of this announcement is the DX-M2 chip. Built on an advanced 2nm process node, it delivers 80 TOPS of computational power. This level of performance is significant for edge devices that require real-time inference without cloud connectivity.

Perhaps more impressive than the specs is the pricing strategy. DeepX CEO Kim Nok-won stated the DX-M2 will launch at a price point below $50. In the current market, comparable AI accelerators often cost significantly more due to complex packaging and supply chain constraints.

This aggressive pricing could disrupt the mid-range edge AI market. It makes sophisticated AI capabilities affordable for consumer electronics manufacturers. Smartphones, laptops, and smart home devices could soon feature powerful local AI processing without inflating retail prices.

Comparison with Current Market Standards

To understand the impact, consider the current landscape. Many existing edge AI chips offer similar TOPS ratings but at higher price points or with greater power demands. For instance, some competing NPU solutions require active cooling or draw excessive battery power.

The DX-M2’s integration with PIM technology mitigates these issues. By reducing the energy cost per operation, it extends battery life in mobile devices. This efficiency is crucial for wearables and portable gadgets where thermal management is challenging.

Future Roadmap: Targeting 1000 TOPS

DeepX is not stopping at the DX-M2. The company has outlined ambitious plans for its next-generation chip, the DX-M3. This future iteration aims to achieve 1000 TOPS of computational power.

Such a leap in performance would place the DX-M3 in direct competition with high-end data center GPUs for certain workloads. However, the focus remains on edge deployment. Achieving this scale while maintaining energy efficiency is a monumental engineering challenge.

The DX-M3 will likely pair with JEDEC-standardized LPDDR6-PIM. Standardization is key here. As JEDEC finalizes the LPDDR6-PIM specifications, more memory manufacturers may enter the market. This could reduce reliance on Samsung and potentially lower costs further through competition.

Implications for Edge AI Development

The roadmap suggests a clear trajectory toward hyper-local AI processing. Developers can expect tools that leverage massive local compute power. This shifts the paradigm from cloud-centric AI to hybrid models where sensitive data stays on-device.

For businesses, this means reduced latency and enhanced privacy. Real-time decision-making becomes feasible in environments with poor connectivity. Autonomous drones, industrial robots, and medical devices stand to benefit immensely from this technological shift.

Industry Context and Strategic Positioning

The global semiconductor industry is increasingly focused on specialized AI hardware. General-purpose CPUs are no longer sufficient for the demands of large language models and computer vision tasks. Companies like NVIDIA dominate the data center, but the edge market remains fragmented.

DeepX’s strategy aligns with broader trends in chiplet-based design and heterogeneous computing. By combining logic and memory in innovative ways, they address specific bottlenecks that traditional architectures cannot solve efficiently.

This move also highlights the growing importance of South Korea in the AI supply chain. With Samsung leading in memory technology and DeepX innovating in logic design, the region is becoming a critical hub for next-generation AI hardware.

What This Means for Stakeholders

For developers, the availability of cheap, powerful edge AI chips opens new possibilities. Applications that previously required cloud processing can now run locally. This reduces operational costs associated with bandwidth and cloud computing fees.

For consumers, this technology promises smarter, more responsive devices. Your smartphone could handle complex photo editing or voice assistants instantly without sending data to a server. Privacy improves as personal data remains on your device.

For investors, DeepX represents a high-growth opportunity in the specialized AI chip sector. Their partnership with Samsung provides a stable foundation, while their aggressive pricing strategy offers a path to rapid market penetration.

Looking Ahead

The commercialization of PIM technology marks a pivotal moment in AI hardware evolution. While challenges remain in software optimization and ecosystem support, the hardware foundation is being laid.

As LPDDR6-PIM standards solidify, we can expect a wave of new products leveraging this technology. DeepX’s early mover advantage could define the next generation of edge AI standards.

Stakeholders should watch for software development kits (SDKs) that fully exploit PIM capabilities. Hardware alone is not enough; efficient algorithms are required to unlock the potential of in-memory computing.

Gogo's Take

• 🔥 Why This Matters: This partnership democratizes high-performance edge AI. By dropping the price of an 80 TOPS chip below $50, DeepX removes the primary barrier to entry for mass-market smart devices. It shifts AI from a cloud-dependent luxury to a ubiquitous, local utility, enhancing privacy and reducing latency for everyday users.
• ⚠️ Limitations & Risks: The heavy reliance on Samsung as the sole PIM supplier creates a single point of failure. If Samsung faces production issues or price hikes, DeepX’s roadmap could stall. Additionally, programming PIM architectures requires new software paradigms; if developer tools lag behind hardware releases, the technology may underperform in real-world scenarios.
• 💡 Actionable Advice: Hardware engineers and AI developers should start experimenting with PIM-compatible frameworks now. Monitor JEDEC’s progress on LPDDR6-PIM standardization to prepare for the DX-M3 era. Businesses should evaluate which of their latency-sensitive applications could benefit from moving processing from the cloud to the edge using these emerging low-cost chips.