PCIe 5.0 Era: Retimer Evolves from Supporting Role to Essential Component

Introduction: The 'Invisible Gatekeeper' of the High-Speed Signal Era

In an age when AI large model training and inference are driving exponential growth in computing demand, core chips such as GPUs and CPUs typically command center stage. Yet deep within servers and data centers, an inconspicuous small chip — the Retimer — is quietly becoming the key variable that determines the performance ceiling of entire systems.

Recently, Kandou CEO Li Zhen elaborated in a detailed conversation on the underlying logic behind the Retimer chip's transformation from a 'supporting player' to an 'essential component' in the PCIe 5.0 era, while offering her own deep insights into the future of the data storage industry.

What Is a Retimer? Why Is It Indispensable in the PCIe 5.0 Era?

In simple terms, a Retimer is a signal relay chip responsible for retiming, equalizing, and regenerating signals along high-speed data transmission links. During the PCIe 3.0 and 4.0 eras, signal rates were relatively low, and the signal attenuation caused by server motherboard traces and connectors remained within manageable limits. Retimer usage was not mandatory — it was more of a 'nice-to-have' optional solution.

But in the PCIe 5.0 era, per-lane data rates have doubled from PCIe 4.0's 16GT/s to 32GT/s, and signal attenuation, jitter, and crosstalk during high-speed transmission have worsened dramatically. Li Zhen pointed out that at this level of signal speed, equalization techniques at the transmitter and receiver alone can no longer guarantee signal integrity. A Retimer must be inserted into the link for signal regeneration; otherwise, the system faces skyrocketing bit error rates or even complete communication failure.

'This is not an option — it is an inevitability dictated by the laws of physics,' Li Zhen summarized regarding the core reason behind the Retimer's role transformation.

Three Driving Forces: AI, Storage, and CXL in Resonance

Rigid Demand from AI Computing Infrastructure

Today, AI accelerator cards represented by NVIDIA H100/B200 have fully adopted PCIe 5.0 interfaces. Large-scale AI training clusters interconnecting thousands of accelerator cards impose extremely stringent requirements on signal integrity. The stability of every single PCIe link directly impacts overall training efficiency, making Retimers an indispensable foundational component in this scenario.

Explosive Growth in High-Speed Storage

Li Zhen placed special emphasis on the strategic importance of data storage in the intelligent world. She believes that 'data storage will become the true cornerstone of the intelligent world.' As NVMe SSDs fully transition to PCIe 5.0, single-drive bandwidth can exceed 14GB/s. Enterprise storage servers typically need to support 24 or more NVMe drive bays, and the convergence of massive high-speed signals has significantly increased Retimer deployment density.

The Rise of the CXL Protocol

The CXL (Compute Express Link) protocol, built on the PCIe 5.0 physical layer, is reshaping memory pooling and heterogeneous computing architectures. CXL devices also rely on PCIe 5.0 physical layer transmission, meaning Retimer application scenarios are expanding beyond traditional CPU-GPU interconnects into emerging fields such as memory expansion and storage acceleration.

Technical Barriers: Far More Than Simple 'Relay'

Although the Retimer's basic function appears straightforward — receive the signal, recover the clock, retransmit — its technical threshold is far higher than outsiders might imagine.

First is the low-latency requirement. The additional latency introduced by a Retimer must be kept to an extremely low level; otherwise, it can trigger the PCIe protocol's completion timeout mechanism and cause system anomalies. Li Zhen revealed that Kandou's Retimer products have achieved industry-leading levels of additional latency control.

Second is power consumption control. Data centers are extremely sensitive to performance per watt, and as an 'additional' component in the link, a Retimer's power consumption must be sufficiently low. This places high demands on the chip's analog front-end design, SerDes architecture, and process node selection.

Third is compatibility verification. Retimers must achieve seamless interoperability with products from dozens of CPU, GPU, SSD, and switch chip manufacturers on the market. Extensive interoperability testing and tuning are critical steps in bringing products to market.

Competitive Landscape: Incumbent Dominance and Domestic Breakthroughs

Currently, the global Retimer market is dominated by a handful of vendors, including Montage Technology, Parade Technologies, and Broadcom. As PCIe 5.0 penetration rates rise rapidly, the market is scaling from the hundreds-of-millions-of-dollars range toward the billion-dollar level, attracting more players including Kandou.

Li Zhen acknowledged that competition in the Retimer market will intensify, but she also emphasized that the moat in this segment lies in 'deep analog IP accumulation and extensive ecosystem validation' — something that cannot be easily replicated in the short term. From a domestic substitution perspective, the Retimer is a category whose strategic value has been severely underestimated — though small, it sits at the critical chokepoint of high-speed data center interconnects.

Bottom-Line Thinking: Technology Development Has No 'Linear Narrative'

When discussing the industry's future, Li Zhen expressed a pragmatic and clear-eyed perspective. She noted, 'No technology development can follow a parabola or a straight line — you need bottom-line thinking.'

This viewpoint is particularly valuable amid the current 'full-speed-ahead' atmosphere in the AI chip industry. PCIe 6.0 is already in the standards-setting phase, with signal rates set to double again to 64GT/s while introducing PAM4 modulation. At that point, both the technical difficulty and market demand for Retimers will reach another level. However, Li Zhen cautioned that a lengthy industrialization cycle exists between standard publication and large-scale commercial deployment, and companies need to find a balance between technology reserves and commercial pacing.

Outlook: From 'Signal Relay' to 'Intelligent Interconnect'

Looking ahead, the Retimer's role may extend well beyond signal regeneration. As data center architectures evolve toward disaggregated designs, Retimers are expected to integrate more intelligent features such as link health monitoring, dynamic power management, and security encryption — evolving from purely analog chips into 'interconnect nodes' with digital intelligence.

As Li Zhen stated, data storage is the cornerstone of the intelligent world, and the Retimer — which ensures high-speed, reliable data flow — is a critical link supporting that cornerstone. In the PCIe 5.0 era and the even higher-speed interconnect eras to come, this once-supporting chip is writing its own leading-role script.