Rambus Launches TDM-Based PCIe 7.0 Switch IP

Rambus has announced a new PCIe 7.0 Switch chip IP featuring time-division multiplexing (TDM) technology, designed to enable massive bandwidth scaling for next-generation AI clusters and high-performance computing networks. The announcement, made on May 5 from the company's California headquarters, positions Rambus at the forefront of the infrastructure race powering the AI revolution.

The new IP block allows system architects to intelligently schedule and multiplex traffic across shared links, maximizing network utilization while reducing complexity. It represents a significant leap beyond simply adding more lanes or endpoints — an approach that Rambus argues is no longer sufficient for modern AI workloads.

Key Takeaways

• What: Rambus PCIe 7.0 Switch IP with built-in TDM technology
• Why it matters: Enables deterministic bandwidth scaling without proportional increases in physical complexity
• Target use cases: AI training clusters, HPC networks, large-scale data center interconnects
• Key benefit: Intelligent traffic scheduling maximizes shared-link utilization across diverse workloads
• Industry context: PCIe 7.0 doubles bandwidth to 128 GT/s compared to PCIe 6.0's 64 GT/s
• Availability: IP licensing for chip designers; no specific silicon timeline disclosed

Why TDM Changes the PCIe 7.0 Game

Traditional PCIe switch architectures allocate dedicated lanes to specific endpoints, which often leads to underutilization when workloads are uneven or bursty. Time-division multiplexing fundamentally changes this dynamic by allowing multiple data streams to share the same physical link through intelligent time-slot scheduling.

In practical terms, TDM means a single high-speed PCIe 7.0 link can serve multiple devices or accelerators without each requiring its own dedicated connection. This is particularly valuable in AI training environments where GPUs, TPUs, and custom accelerators generate highly variable traffic patterns.

The approach mirrors techniques long used in telecommunications but is now being adapted for the ultra-low-latency, ultra-high-bandwidth world of chip-to-chip interconnects. By bringing TDM to PCIe 7.0, Rambus enables what it calls 'deterministic bandwidth scaling' — the ability to predictably expand capacity without the exponential growth in physical infrastructure that traditional approaches demand.

Rambus Executive Highlights AI-Driven Architecture Shift

Simon Blake-Wilson, Senior Vice President and General Manager of Silicon IP at Rambus, framed the announcement in the context of AI's transformative impact on system design. 'AI's accelerating development is fundamentally reshaping system architectures,' Blake-Wilson stated. 'Simply adding more lanes or endpoints is no longer enough.'

His comments underscore a growing industry consensus that the traditional approach of scaling PCIe — adding more lanes, more switches, and more endpoints — is hitting diminishing returns. The power, cost, and complexity overhead of brute-force scaling makes it impractical for the thousand-GPU-plus clusters that leading AI companies now deploy.

Blake-Wilson emphasized that the TDM-enabled switch IP gives system architects 'greater freedom to efficiently and deterministically scale bandwidth while reducing complexity and improving overall system utilization.' He called this capability 'critical for the scale-out of next-generation advanced AI clusters and HPC networks.'

PCIe 7.0: The Bandwidth Backbone for AI Infrastructure

PCIe 7.0, finalized by the PCI-SIG consortium, represents the next major leap in peripheral interconnect technology. Key specifications include:

• Data rate: 128 GT/s (gigatransfers per second), double PCIe 6.0's 64 GT/s
• Bandwidth per lane: Up to 242 GB/s in x16 configuration
• Encoding: PAM-4 (Pulse Amplitude Modulation with 4 levels)
• Expected silicon: First chips anticipated in 2026-2027 timeframe
• Backward compatibility: Maintains compatibility with all previous PCIe generations

At these speeds, the efficiency of switching and routing becomes paramount. Every percentage point of link utilization translates to significant real-world performance gains. This is precisely where Rambus's TDM approach delivers its value — squeezing maximum throughput from every physical link rather than requiring additional hardware.

Compared to PCIe 5.0, which is currently the mainstream standard in data centers, PCIe 7.0 offers an 8x improvement in raw bandwidth per lane. This generational leap is being driven almost entirely by AI workload demands, where massive models require unprecedented amounts of data movement between processors, memory, and storage.

How TDM Enables Massive AI Cluster Scale-Out

Modern AI training clusters face a fundamental interconnect challenge. As the number of accelerators grows from hundreds to thousands — and eventually tens of thousands — the switching fabric connecting them becomes a critical bottleneck. Traditional PCIe switch architectures struggle with this scale for several reasons:

• Port count limitations: Physical switch chips can only support a finite number of ports
• Bandwidth fragmentation: Dedicated lanes to idle or low-utilization endpoints waste capacity
• Latency variability: Congestion on shared resources creates unpredictable performance
• Power consumption: More physical links mean more power for transceivers and routing logic
• Cost escalation: Each additional physical connection adds board area, signal integrity challenges, and manufacturing cost

TDM addresses these issues by virtualizing the physical link layer. Instead of dedicating a physical lane to each endpoint, the switch dynamically allocates time slots based on real-time demand. High-priority or bandwidth-hungry accelerators receive more time slots, while idle connections consume zero bandwidth.

This approach is conceptually similar to how modern network switches handle Ethernet traffic, but applied at the much tighter latency and bandwidth requirements of PCIe. The result is a more efficient, more scalable, and more cost-effective switching fabric — exactly what AI infrastructure builders need.

Industry Context: The Race to Build AI-Scale Interconnects

Rambus is not alone in recognizing that interconnect technology must evolve to match AI's insatiable appetite for bandwidth. The broader industry is seeing intense activity across multiple fronts.

NVIDIA has invested heavily in its NVLink and NVSwitch technologies, which provide proprietary high-bandwidth interconnects between GPUs. The latest NVLink generation in the Blackwell architecture delivers 1.8 TB/s of bidirectional bandwidth. However, NVLink is proprietary and limited to NVIDIA hardware.

Intel continues to push CXL (Compute Express Link) as a complementary technology to PCIe, enabling memory sharing and coherency across heterogeneous compute elements. CXL 3.0 already supports switching and fabric capabilities.

Broadcom and Microchip are major players in the PCIe switch silicon market, with products spanning PCIe 4.0 through 5.0 generations. Both companies are expected to pursue PCIe 7.0 switch solutions.

Rambus's strategy differs from these competitors in a crucial way: as an IP licensor rather than a chip manufacturer, Rambus sells its switch designs to other semiconductor companies who then integrate them into their own products. This means Rambus's TDM-enabled PCIe 7.0 switch technology could potentially appear in chips from multiple vendors, amplifying its market impact.

What This Means for AI Infrastructure Builders

For companies designing next-generation AI training and inference infrastructure, Rambus's announcement signals several important developments.

First, the PCIe 7.0 ecosystem is maturing faster than many expected. With Rambus already offering licensable switch IP, chip designers can begin integrating PCIe 7.0 switching into their product roadmaps today, potentially accelerating time-to-market for PCIe 7.0 silicon.

Second, the TDM approach suggests a shift in how system architects think about interconnect scaling. Rather than designing for peak bandwidth on every link, architects can now design for aggregate bandwidth across shared links — a more efficient and cost-effective approach that could reduce both bill-of-materials costs and power consumption.

Third, the emphasis on 'deterministic' scaling is significant for enterprise AI deployments where predictable performance matters. Unlike best-effort traffic management, TDM provides guaranteed time slots, ensuring that critical workloads receive their required bandwidth regardless of overall system load.

Looking Ahead: PCIe 7.0 Timeline and Adoption

While PCIe 7.0 silicon is not expected to reach production until 2026 or 2027, the IP licensing phase is already underway. Chip designers typically begin integrating complex IP blocks like PCIe switch controllers 2-3 years before their target product ships.

Rambus's early entry into the PCIe 7.0 switch IP market gives it a potential first-mover advantage. Companies licensing this IP today could be among the first to deliver PCIe 7.0 switch silicon when the broader ecosystem — including processors, accelerators, and motherboards — is ready.

The AI infrastructure market shows no signs of slowing down. With hyperscalers like Microsoft, Google, Amazon, and Meta spending tens of billions of dollars annually on AI compute infrastructure, demand for faster, more efficient interconnect solutions will only intensify. Rambus's TDM-enabled PCIe 7.0 switch IP arrives at precisely the right moment to capture this demand.

As the industry moves toward clusters of 100,000+ accelerators, the switching fabric connecting them becomes arguably the most critical component in the entire system. Rambus is betting that TDM is the key to making that fabric both scalable and efficient — a bet that could define the next era of AI infrastructure.